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ADuM1410/ADuM1411/ADuM1412
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM141x ARWZ
Minimum Pulse Width 2
Maximum Data Rate 3
PW
1
1000
ns
Mbps
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Propagation Delay 4
Pulse Width Distortion, |t PLH ? t PHL | 4
Propagation Delay Skew 5
Channel-to-Channel Matching 6
t PHL , t PLH
PWD
t PSK
t PSKCD/OD
20
65
100
40
50
50
ns
ns
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
ADuM141x BRWZ
Minimum Pulse Width 2
Maximum Data Rate 3
PW
10
100
ns
Mbps
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Propagation Delay 4
Pulse Width Distortion, |t PLH ? t PHL | 4
t PHL , t PLH
PWD
20
30
50
5
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
C L = 15 pF, CMOS signal levels
Propagation Delay Skew 5
Channel-to-Channel Matching,
t PSK
t PSKCD
30
5
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Codirectional Channels 6
Channel-to-Channel Matching,
t PSKOD
6
ns
C L = 15 pF, CMOS signal levels
Opposing-Directional Channels 6
All Models
Output Rise/Fall Time (10% to 90%)
t R /t F
2.5
ns
C L = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
|CM H |
25
35
kV/μs
V Ix = V DD1 or V DD2 , V CM = 1000 V,
at Logic High Output 7
transient magnitude = 800 V
Common-Mode Transient Immunity
|CM L |
25
35
kV/μs
V Ix = 0 V, V CM = 1000 V,
at Logic Low Output 7
transient magnitude = 800 V
Refresh Rate
f r
1.2
Mbps
Input Enable Time 8
Input Disable Time 8
Input Dynamic Supply Current
t ENABLE
t DISABLE
I DDI (D)
0.12
2.0
5.0
μs
μs
mA/
V IA , V IB , V IC , V ID = 0 V or V DD1
V IA , V IB , V IC , V ID = 0 V or V DD1
per Channel 9
Mbps
Output Dynamic Supply Current
per Channel 9
I DDO (D)
0.04
mA/
Mbps
1
2
3
4
5
6
7
8
9
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V DD1 and V DD2 supply currents as a function of data rate for ADuM1410 / ADuM1411 / ADuM1412 channel configurations.
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is
measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal.
t PSK is the magnitude of the worst-case difference in t PHL or t PLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
|CM H | is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2 . |CM L | is the maximum common-mode voltage slew rate
that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
Input enable time is the duration from when V DISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V DISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL 2 logic state (see Table 14).
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. J | Page 4 of 24
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